Digitizing Signals and Discretization
The heart of a direct conversion receiver is the analog-to-digital converter (A/D converter or ADC), that samples analog signal in order to transform them into the digital domain. Sampling includes two tasks: discretization in time and discretization of the amplitude. Discretization in the time domain is determined by the sampling frequency, whereas discretization of the amplitude is determined by the bit width of the digital values, that can be seen as a “rounding” operation, often called “quantization”. The analog signal is a continuous waveform – its sampled digital signal is just a list of numbers. Digital signals always need additional information on the sampling frequency fs to carry meaningful information.
The Sampling Theorem
Shannon’s sampling theorem answers the question, how fast the sample rate fs for the AD conversion must be in order not to lose information: The sampling frequency f_{s} must be higher than twice the frequency (or highest frequency component) of the analog signal f_{analog} .
f_{s} \geq 2 f_{analog}If this rule is fulfilled, the digital samples contain the full information on the analog waveform. This means that the digital signal can be perfectly converted back to the original analog signal. This could be done by a sample-and-hold circuit, that first creates an intermediate signal looking similar like a staircase. In a second step a (ideal) low-pass filter with an edge frequency of f_{s}/2 creates a smooth waveform.
If the sampling theorem is violated, i.e. analog signals are faster than half the sampling rate f_{s} , the so-called effect of “aliasing” occurs. In this case the digitized signal represents an analog signal with a different lower “aliasing” frequency. A DA converter with a sample & hold circuit and low-pass filter would interpolate the signal at this lower frequency. In general an analog signal of frequency f_{analog} has in the digital domain the (aliasing) frequency
f=|nf_s-f_{analog}|
where n is an integer chosen such that f<f_{s}/2
The analog spectrum can be divided in so-called Nyquist zones, that represent slices of bandwidth f_{s}/2 . Frequencies of the same Nyquist zone alias unambiguously to digital frequencies (independent of the fulfillment of the sampling theorem). The sampling theorem is fulfilled, if the analog frequencies are exclusively located in the first Nyquist zone.
The sampling theorem implies an important information for the digital signal processing of SDRs: There is a strong relationship between SDR bandwidth and the data rates (corresponding to the sampling frequency). The larger the bandwidth is, the higher data rates generated are in the digital domain. Therefore high bandwidths pose a challenge not only to analog-to-digital conversion, but also to the succeeding DSP.
Undersampling
In practical applications aliasing is not always a problem, but can also be used for sampling frequencies above f_{s}/2 . This technique, called undersampling (or sometimes IF or bandpass sampling) samples too slow and violates the sampling theorem, such that aliasing occurs intentionally. Then frequencies above f_{s}/2 appear at lower frequencies < f_{s}/2 . In this sense undersampling exhibits the same behaviour as a mixer, as it shifts signals in frequency. Undersampling works perfectly fine, if all analog input signals reaching the AD converter belong to only one Nyquist zone. For that purpose a proper band-pass filter may be required before AD conversion, that cuts off all frequencies of other Nyquist zones. If a frequency band is to be undersampled, that spans over more than one Nyquist zone (e.g. if the signal frequencies lie around nf_{s}/2 ), it may be advantageous to change the sampling frequency.
The Influence of Clock Jitter on SNR
A sometimes overlooked property is the quality of the clock source, that generates the sampling clock for the analog-to-digital converter. Sampling clock jitter introduces additional noise, because due to the jitter the analog signal is (randomly) sampled slightly too early or too late. This results in a small random amplitude error, as depicted in the image below. In analog-to-digital conversion this additional noise contributes to the overall SNR. The following formula describes the theoretically maximum SNR in dB, that can be achieved for a given clock jitter t_{jitter} .
SNR = 20 \,log \left( \frac{1}{2 \pi f_{analog} t_{jitter} } \right)
The amount of noise introduced by jitter is not only dependent on the clock jitter itself, but also on the frequency f_{analog} of the analog signal. Fast analog signals are more susceptible to clock jitter noise. This is because the waveform changes more rapidly and therefore even a small deviation in the sampling time leads to large amplitude error.
