The Direct Sampling SDR Architecture

The traditional radio receiver uses analog processing, i.e. analog mixers, filters and amplifiers to convert the incoming RF analog signal from the antenna to baseband, such as audio frequencies. In contrast, software defined radios (for simplicity I use this term for any kind of digital radio) rely on digital signal processing (DSP) techniques for reception. This DSP functionality includes e.g. mixing, filtering, local oscillators or amplification in the digital domain. It is implemented in software running on a processor or as digital circuits in microchips (FPGAs or ASICs).

SDR Receiver Architectures

In a SDR the interface between the analog and the digital world is the AD converter. The AD converter can be placed at different stages of a receiver, thus determining which parts of the receivers are realized in the analog or digital domain. Today most receivers are a combination of analog down conversion followed by the AD converter and digital processing.

Historically the AD converter moved from the end of the reception path (where bandwidth is low) further towards the front (where bandwidth usually is higher). This is desirable, because digital signal processing is largely superior to analog processing (see Advantages of DSP). For this reason it is only logical to put the AD converter as close as possible to the antenna. The ultimate concept is called direct sampling, sometimes also “all-digital receiver“, “digital radio” or “antenna-to-bits“.

In a direct sampling receiver the antenna is more or less directly connected to the AD converter with no analog down conversion. Of course connecting the antenna to the AD converter directly may not be a very good idea, because aliasing will likely spoil the signals of interest (see AD conversion basics). Therefore even a direct sampling receiver typically includes an analog filter and usually a preamplifier. The analog filter serves as anti-aliasing filter and can further reduce unwanted out-of-band signals. The preamplifier improves receiver sensitivity, that is sometimes limited by internal noise of AD converters otherwise.

Advantages of Direct Sampling SDRs

Digital Signal Processing: Direct sampling receivers perform as much receiver functions as possible using DSP instead of analog circuits. There are many advantages of digital processing: easy to implement steep filters, extremely pure LO signals using direct digital synthesis, distortionless mixing and amplification, no extra noise and no EMC problems. High precision number representations can implement DSP functions with almost arbitrary accuracy. To summarize: Once the signal has been digitized, it is not prone to further degradation anymore. The only performance bottleneck in a direct sampling radio is the AD converter. It is important to carefully select the AD converter, since it determines the overall performance in of the radio in terms of linearity, sensitivity and bandwidth.

Challenges of Direct Sampling SDRs

AD Converter Resolution: In direct sampling the frequencies of the signals to be digitized are comparably large, because no analog down conversion is performed. This requires fast AD converters, that are often available only with smaller bit resolution (ENOBs).

Clock Jitter and SNR: For direct sampling the phase noise or jitter of the sampling clock becomes important. Clock jitter introduces extra noise, which may exceed the ADC’s SNR. The amount of extra noise depends on the frequency of the analog input signal. Since these frequencies are comparably large in direct sampling receivers, it is important to use high-performance clock generators with extra low jitter (see AD conversion basics).

Data Rates: Direct sampling receivers have to deal with high bandwidths and thus high sampling rates, that may create extremely high data rates for DSP. Therefore direct sampling is applied more widely to lower frequencies and may be prohibitive for higher frequencies. The Panoradio e.g. creates a input data rate of 16 bit x 250 MHz = 4 GBit/s and internally up to 2 x 22 bit (IQ) x 250 MHz = 11 GBit/s. Usually these data rates cannot be handled by a PC or other processor based system. Instead they require the implementation of highly-parallel digital circuits in FPGAs. Recent system on chips like Xilinx’s RFSoC can operate up to eight 14-Bit ADC running at 5 Gsps. This creates an input data stream of up to 8 x 14 x 5 Gsps = 560 GBit/s, that is extremly hard to process even with modern FPGAs.