June 25, 2024

Powerful Hardware for SDR: The Zynq and the Zedboard

This an excerpt of my more extensive paper on Xilinx’s Zynq System-on-Chip for Software Defined Radio processing from 2018:

“The Xilinx Zynq: A Modern System on Chip for Software Defined Radios”

Software defined radios heavily rely on digital signal processing, that needs to be executed on powerful hardware platforms. SDRs require a wide range of different tasks, that have to be performed at different speed and data thoughput.

Slow tasks, that can be executed on a processor in software:

  • Demodulation of different modes
  • Automatic gain control
  • Audio / baseband filtering
  • Control of the receiver functions
  • Providing a user inferface (UI)

High speed tasks, that usually require FPGAs:

  • Wide band downconversion
  • High-speed filtering
  • High-speed FFT
  • Parallel demodulation of many signals

The ideal hardware for SDR is therefore a combination of processor and FPGA.

The Zynq

Recent development in microelectronic has led to a new kind of microchips, that combine an FPGA and a processor on a single chip. The FPGA manufacturer Xilinx has presented the Zynq Device, whereas its competitor Altera introduced the Altera SoC series. Both chips are very similar in system structure and performance. The Panoradio uses the Xilinx Zynq, but many details described here are also applicable to Altera SoCs.

The Zynq SoC contains a dual ARM Core A9, an FPGA and additional blocks for different I/O (e.g. DDR3 memory interface, USB, SD Card Slot). There are up to 3000 possible connections between the processor and the FPGA, which are programmable and allow fast transmission of data. This is a big advantage over a separate combination of FPGA and processor on a PCB, where the number of possible connections is small and can hardly be changed after PCB design. The Zynq comes in six different sizes (Z-7010 to Z-7100). All contain a dual ARM A9, but the FPGA part has largely different sizes.

Zynq device structure
The Zynq SoC features a processor and a FPGA as well as I/O peripherals support

Programming of the Zynq involves two tasks: Programming the processor and designing the digital circuit for the FPGA. These two tasks can be done nearly independently by different tools.

Programming the Processors

The processor can be programmed either bare metal or using an operating system. Bare metal refers to programming the ARM processor directly in C without any operating system using e.g. the Xilinx SDK tool. However it is strongly recommended to use an operating system like Linux, which hides many details of the processor and provides easy access to interfaces as well as standard software.

As an operating system a linux distribution (e.g. Ubuntu/Linaro) can be installed on a SD Card (link), which also serves as a file system. Access to the processor can be gained through the network interface (SSH or RDP) or by directly attaching monitor, keyboard and mouse (use as a standalone system). Then standard software can be used (provided from the linux package manager or compiled by hand). Software like SciLab (mathematical toolbox) or the powerful demodulation software Fldigi can be installed directly via package manager. Programming can be done using many languages, like C/C++, Qt, Python, Java etc. An editor, IDE or compiler for programming can directly run on the Zynq to avoid cumbersome cross compilation.

desktop view of linux running on the Zynq
Linux with LXDE desktop running on the Zynq

FPGA Design

The more challenging part is the hardware design for the FPGA. Here Xilinx provides its design tool called ”Vivado”. The basic functionality of Vivado is free of cost, an additional license for the debugging functionalities (Vivado Logic Analyzer) is included in the Zedboard. These tools are sufficient for most of the designs for the Zynq.

SDR design can be done by using the Vivado Block Design, which is a top level schematic, that connects different blocks. The blocks contain the main functionality and can be designed in different ways. One is using a hardware description language like VHDL or Verilog. The other option is to rely on high level synthesis, like Vivado HLS or Matlab based tools (System Generator, HDL Coder), that basically try to convert C or Matlab code into a digital circuit.

Xilinx Vivado design GUI example
Vivado Block Designer

It is worth to mention, that Xilinx offers some predefined hardware components, that are very useful to build a SDR: A sine signal generator based on direct digital synthesis (DDS) is available, that can be parameterized. Frequency range, resolution, bitwidths, clock speed and spurious-free dynamic range (SFDR) can be chosen. SFDRs of 150 dB can be easily obtained. Another useful hardware block is the FIR filter compiler, that allows for easy implementation of FIR filters. Many hardware parameters can be chosen, the filter coefficient design itself can be done using e.g. Matlab.

Designing the hardware for FPGA requires good knowledge and experience in hardware design and digital circuits.

How the Zynq Interconnect Works

As mentioned above the Zynq provides several thousand interconnections between the processor and the FPGA for the exchange of data. It is worth to mention a few words on how these interconnect works.

The interconnect is a memory mapped interface. That means that a part of the processor’s memory is virtually connected to a 32 Bit register in the FPGA. The processor can write data to this special memory part, that is transferred to the FPGA registers. Or it can read the registers in the FPGA by reading data from the memory. From an FPGA point of view data transfer is done by just reading and writing to the 32 bit registers.

Schematics showing interconnects between processor and FPGA
Interconnect between processor and FPGA

Although moving data sounds not too complicated and is for a programmer, it involves a quite complex process based on a standard called AXI, which is fortunately mostly hidden to the user.

If a large amount of data is to be transferred, direct memory access (DMA) can be used. This allows much faster transmission of data by using the high performance (HP) or accelerated coherence port (ACP), see here for more information.

The Zedboard

The Zedboard is a low-cost evaluation board for the Xilinx Zynq SoC. It is ideal for experimenters, because it provides a lot of interfaces and peripherals. It is an ideal platform for many different applications like image processing, control systems, acceleration of algorithms – and software defined radio. A lot of technical information including schematics, tutorials and reference designs are available at https://www.avnet.com/wps/portal/us/products/avnet-boards/.

In detail the Zedboard features:

  • 512 MB DDR3 Memory
  • Gigabit Ethernet
  • HDMI interface
  • VGA connector
  • OLED display
  • SD card slot
  • GPIO pins, buttons and LEDs
  • FMC connector
  • Audio Interface / Sound Codec ADAU 1761
  • onboard clock generators

These peripherals make the Zedboard a fully standalone system. Monitor, mouse, keyboard and headphone can be connected, as well as an internet connection established.

Photograph of the Zedboard

Since the Zedboard itself does not contain any ADC or DAC suitable for SDR, a radio module needs to be connected. The FMC connector is ideal for that. Many companies like Analog Devices, Texas Instruments or Linear Technology offer daughter board with an FMC interface. These boards can be easily connected to the Zedboard.

An advantage of the Zedboard over many other SDR platform is, that the radio module is not fixed. It can be chosen according to the user’s requirements and available budget. It is easy to change the FMC board and create a radio with a completely new ADC/DAC system.

Besides the ”classical” Zedboard more Zynq boards appeared on the market. The MicroZed and the Zybo should be mentioned, since they are much cheaper and offer similar functionality. But it needs to be pointed out that these boards do not have a full FMC connector. This makes it harder to attach ADCs and DACs to create a full software defined radio platform.

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